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| Microelectronics Inc. BRIGHT BM29F400T/BM29F400B 4MEGABIT (512K x 8/ 256K x 16) 5VOLT SECTOR ERASE CMOS FLASH MEMORY GENERAL DESCRIPTION The BM29F400 is an 4 Megabit, 5.0 volt-only CMOS Flash memory device organized as a 512 Kbytes of 8-bits each, or 256 Kbytes of 16 bits each. The device is offered in standard 48-pin TSOP package. It is designed to be programmed and erased in-system with a 5.0 volt power-supply and can also be reprogrammed in standard EPROM programmers. With access times of 90 nS, 120 nS, and 150 nS, the BM29F400 has separate chip enable CE , write enable WE , and output enable OE controls. BMI's memory devices reliably store memory data even after 100,000 program and erase cycles. The BM29F400 is entirely pin and command set compatible with the JEDEC standard for 4 Megabit Flash memory devices. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. The BM29F400 is programmed by executing the program command sequence. This will start the internal byte/word programming algorithm that automatically times the program pulse width and also verifies the proper cell margin. Erase is accomplished by executing either the sector erase or chip erase command sequence. This will start the internal erasing algorithm that automatically times the erase pulse width and also verifies the proper cell margin. No preprogramming is required prior to execution of the internal erase algorithm. Sectors of the BM29F400 Flash memory array are electrically erased via Fowler-Nordheim tunneling. Bytes/words are programmed one byte/word at a time using a hot electron injection mechanism. The BM29F400 features a sector erase architecture. The device memory array is divided into one 16 Kbytes, two 8 Kbytes, one 32 Kbytes, and seven 64 Kbytes. Sectors can be erased individually or in groups without affecting the data in other sectors. Multiple sector erase and full chip erase capabilities add flexibility to altering the data in the device. To protect this data from accidental program and erase, the device also has a sector protect function. This function hardware write protects the selected sector(s). The sector protect and sector unprotect features can be enabled in a PROM programmer. For read, program and erase operation, the BM29F400 needs a single 5.0 volt power-supply. Internally generated and well regulated voltages are provided for the program and erase operation. A low Vcc detector inhibits write operations on loss of power. End of program or erase is detected by the Ready/Busy status pin, Data Polling of DQ7, or by the Toggle Bit I feature on DQ6. Once the program or erase cycle has been successfully completed, the device internally resets to the Read mode. The BM29F400 also has a hardware RESET pin. Driving the RESET pin low during execution of an Internal Programming or Erase command will terminate the operation and reset the device to the Read mode. The RESET pin may be tied to the system reset circuitry, so that the system will have access to boot code upon completion of system reset, even if the Flash device is in the process of an Internal Programming or Erase operation. If the device is reset using the RESET pin during an Internal Programming or Erase operation, data in the address locations on which the internal state A Winbond Company -1- Publication Release Date: December 1999 Revision A2 Microelectronics Inc. BRIGHT BM29F400T/BM29F400B machine is operating will be erroneous. Thus, these address locations will need rewriting after the device is reset. FEATURES * 5.0V +/- 10% Program and Erase - Minimizes system-level power requirements High performance - 90 nS access time Compatible with JEDEC-standard Commands - Uses software commands, pinouts, and packages following industry standards for single power supply Flash memory Typically 100,000 Program/Erase Cycles Sector Erase Architecture - One 16 Kbytes, two 8 Kbytes, one 32 Kbytes, and seven 64 Kbytes - Any combination of sectors can be erased concurrently; also supports full chip erase * RESET - Hardware pin resets the internal state machine to the read mode * * Internal Erase Algorithms - Automatically erases a sector, any combination of sectors, or the entire chip Internal Programming Algorithms - Automatically programs and verifies data at a specified address Low Power Consumption - 20 mA typical active read current for Byte Mode - 28 mA typical active read current for Word Mode - 30 mA typical write/erase current * * * * * Erase Suspend/Resume - Suspend a sector erase operation to allow a data read in a sector not being erased within the same device Ready/Busy - RY/BY output pin for detection of programming or erase cycle completion * * Sector Protection - Hardware method disables any combination of sectors from a program or erase operation Boot Code Sector Architecture * FAMILY PART NO. Maximum Access Time (nS) CE (E) Access time (nS) OE (G) Access time (nS) -90 90 90 35 -120 120 120 50 -150 150 150 60 *This speed is available with Vcc = 5V +/- 5% variation -2- Microelectronics Inc. BRIGHT BM29F400T/BM29F400B PIN CONFIGURATIONS PIN DESCRIPTION A0-A17 DQ0-DQ14 DQ15/A-1 CE OE WE VSS RESET A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET NC NC RY/BY NC A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE Vss CE A0 Standard TSOP RY/BY VCC BYTE NC Address Inputs Data Input/Output Data Input/Output, Address Max. Chip Enable Output Enable Write Enable Device Ground Hardware RESET Pin, Active Low Ready/Busy Status Output Device Power Supply Selects 8-bit or 16-bit Mode Not Internally Connected BLOCK DIAGRAM Vcc Vss /WE /BYTE /RESET RY/BY Buffer State Control Command Register DQ0-DQ15 Erase Boltage Generator Input/Output Buffers PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch /CE /OE STB Y-Decodor Vcc Detector A0-A16 A-1 Address Latch X-Decoder Y-Gating Cell Matrix Timer A Winbond Company -3- Publication Release Date: December 1999 Revision A2 Microelectronics Inc. BUS OPERATION Table 1. Bus Operations (BYTE = VIH)(1) OPERATION Electronic ID Manufacturer(2) Electronic ID Device(2) Read(3) Standby Hardware Reset Output Disable Write Verify Sector Protect(2) Temporary Sector Unprotect CE L L L H X L L L X OE L L L X X H H L X WE H H H X X H L H X A0 L H A0 X X X A0 L X BRIGHT BM29F400T/BM29F400B A1 L L A1 X X X A1 H X A6 L L A6 X X X A6 L X A9 VID VID A9 X X X A9 VID X DQ0-DQ15 Code Code DOUT High Z High Z High Z DIN(4) Code X H H H H L X H H RESET VID Notes: 1. L = VIL, H = VIH, X = Don't Care. See DC Characteristics for voltage levels. 2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 6. 3. WE can be VIL if CE is VIL, OE at VIH initiates the write operations. 4. Refer to Table 6 for valid DIN during a write operation. Table 2. Bus Operations (BYTE = VIL)(1) OPERATION Electronic ID Manufacturer(2) Electronic ID Device(2) Read(3) Standby Hardware Reset Output Disable Write Verify Sector Protect(2) Temporary Sector Unprotect CE L L L H X L L L X OE L L L X X H H L X WE A0 L H A0 X X X A0 L X A1 L L A1 X X X A1 H X A6 L L A6 X X X A6 L X A9 VID VID A9 X X X A9 VID X DQ0-DQ7 Code Code DOUT High Z High Z High Z DIN(4) Code X DQ8-DQ15 High Z High Z High Z High Z High Z High Z High Z High Z High Z RESET H H H H L H H H VID H H H X X H L H X Notes: 1. L = VIL, H = VIH, X = Don't Care. See DC Characteristics for voltage levels. 2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 6. 3. WE can be VIL if CE is VIL, OE at VIH initiates the write operations. 4. Refer to Table 6 for valid DIN during a write operation. -4- Microelectronics Inc. BRIGHT BM29F400T/BM29F400B Table 3. Sector Protection Verify Electronic ID Codes TYPE Manufacturer Code 29F400T 29F400 29F400B Sector Protection Byte Word Byte Word Sector Address VIL VIH VIL Note: Outputs 01H at protected sector addresses, and outputs 00H at unprotected addresses. A17-A12 X X X A6 VIL VIL VIL A1 VIL VIL VIL A0 VIL VIH VIH Code (Hex) ADH 23H 22,23H ABH 22 ABH 01H(1) Table 4. Sector Address Tables (BM29F400T) A17 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Notes: 1. The address range is A17:A-1 if in byte mode ( BYTE = VIL). 2. The address range is A17:A0, if in word mode ( BYTE = VIH). 0 0 0 0 1 1 1 1 1 1 1 A16 0 0 1 1 0 0 1 1 1 1 1 A15 0 1 0 1 0 1 0 1 1 1 1 A14 X X X X X X X 0 1 1 1 A13 X X X X X X X X 0 0 1 A12 X X X X X X X X 0 1 X (x8) Address Range 00000H -0FFFFH 10000H -1FFFFH 20000H -2FFFFH 30000H -3FFFFH 4 0000H-4FFFFH 50000H -5FFFFH 60000H -6FFFFH 70000H -77FFFH 78000H -79FFFH 7A000H -7BFFFH 7C000H- 7FFFFH (x16) Address Range 00000H- 07FFFH 08000H- 0FFFFH 10000H- 17FFFH 18000H- 1FFFFH 20000H- 27FFFH 28000H- 2FFFFH 30000H- 37FFFH 38000H- 3BFFFH 3C000H- 3CFFFH 3D000H- 3DFFFH 3E000H- 3FFFFH Table 5. Sector Address Tables (BM29F400B) SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Notes: 1. The address range is A17:A-1 if in byte mode ( BYTE = VIL). 2. The address range is A17:A0, if in word mode ( BYTE = VIH). A17 0 0 0 0 0 0 0 1 1 1 1 A16 0 0 0 0 0 1 1 0 0 1 1 A15 0 0 0 0 1 0 1 0 1 0 1 A14 0 0 0 1 X X X X X X X A13 0 1 1 X X X X X X X X A12 X 0 1 X X X X X X X X (x8) Address Range 00000H-03FFFH 04000H-05FFFH 06000H-07FFFH 08000H-0FFFFH 10000H-1FFFFH 20000H-2FFFFH 30000H-3FFFFH 40000H-4FFFFH 50000H-5FFFFH 60000H-6FFFFH 70000H-7FFFFH x16) Address Range 00000H-01FFFH 02000H-02FFFH 03000H-03FFFH 04000H-07FFFH 08000H-0FFFFH 10000H-17FFFH 18000H-1FFFFH 20000H-27FFFH 28000H-2FFFFH 30000H-37FFFH 38000H-3FFFFH A Winbond Company -5- Publication Release Date: December 1999 Revision A2 Microelectronics Inc. Electronic ID Mode BRIGHT BM29F400T/BM29F400B The Electronic ID mode allows the reading out of a binary code from the device and will identify its manufacturer and device type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5V to 12.5V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are don't cares except A0, A1, and A6 (see Table 3). Manufacturer and device codes may also be read via the command register; for instance, when the BM29F400 is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 6 (refer to Electronic ID Command section). Byte 0 (A0 = VIL) represents the manufacturer's code (Bright Microelectronics = ADH) and byte 1 (A0 = VIH) the device identifier code (BM29F400T = 23H and BM29F400B = ABH for 8-bit mode; BM29F400T = 2223H and BM29F400B = 22ABH for 16-bit mode). These two byte words are given in Table 3. To read the proper device codes when executing the Electronic ID, all identifiers for manufacturer and device will exhibit odd parity with the MSB (DQ7) defined as the parity bit. A1 must be VIL (see Table 3). Read Mode The BM29F400 has three control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. As shown in Table 1, WE should be held at VIH, except in Write mode and Enable Sector Protect mode. Address access time (tACC) is equal to the delay from stable addresses to valid output data. Chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. Output enable access time is the delay from the falling edge of OE to valid data at the output pins (assuming the addresses have been stable for at least tACC-tOE time). Standby Mode and Hardware RESET Standby Mode The BM29F400 has two methods for implementing standby mode. The first method requires use of both the CE pin and the RESET pin. The second method only requires use of the RESET pin. When using both pins, a CMOS standby mode is achieved when both CE and RESET are held at Vcc 0.5V. In this condition, the current consumed is typically less than 100 A. A TTL standby mode is achieved with both CE and RESET held at VIH. In this condition, the typical current required is reduced to 200 A. The device can be read with standard access time (tCE) from either of these two standby modes. When using the RESET pin only, a CMOS standby mode is achieved with RESET held at VSS 0.5V. In this condition, the current consumed is typically less than 100 A. A TTL standby mode is achieved with RESET held at VIL. In this condition, the typical current required is reduced to 1 mA. Once the RESET pin is taken high, the device requires 500 nS of wake-up time before outputs are valid for a read access. -6- Microelectronics Inc. BRIGHT BM29F400T/BM29F400B If the device is deselected during programming or erase, the device will draw active current until the programming or erase operation is completed. In the standby mode the outputs are in a high impedance state, independent of the OE input. Output Disable Mode With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state. It is shown in Table 1 that CE = VIL and WE = VIH for Output Disable. This is to differentiate Output Disable mode from Write mode and to prevent inadvertent writes during Output Disable. Program and Erase Modes Device programming and erase are accomplished via the command register. Contents of the register serve as inputs to the internal state machine. Outputs of the state machine dictate the function of the device. The command register itself does not occupy any addressable memory locations. The register is a latch used to store the commands along with the addresses and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE , whichever happens later, while data is latched on the rising edge of WE or CE , whichever happens first. Standard microprocessor write timings are used. Refer to AC Characteristics for Programming/Erase and their respective Timing Waveforms for specific timing parameters. Enable Sector Protect and Verify Sector Protect Modes The BM29F400 has a hardware Sector Protect mode that disables both Programming and Erase operation to the protected sector(s). There are total of 11 sectors in this device. The sector protect feature is enabled using the programming equipment at the user's site. The device is shipped from the BMI factory with all sectors unprotected. To verify programming of the protection circuitry, the programming equipment must force VID on the address pin A9 with CE and OE at VIL and WE at VIH. As shown in Table 2, scanning the sector addresses while (A6, A1 and A0) = (0, 1, 0) will produce a 01H code at the device output pins for a protected sector. In the Verify Sector Protect mode, the device will read 00H for an unprotected sector. In this mode, the lower order addresses, except for A0, A1 and A6, are don't care. Address locations with A1 = VIL are reserved for Electronic ID manufacturer and device codes. It is also possible to determine if a sector is protected in-system by writing the Electronic ID command (described in the Electronic ID command section below.) Temporary Sector Unprotect Mode The BM29F400 has a Temporary Sector Unprotect feature that allows the protect feature to be temporarily suspended to change data in a protected sector in-system. The Temporary Sector Unprotect mode is activated by setting the RESET pin to VID (11.5V-12.5V). In this mode, protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET pin, all previously protected sectors will be protected. Refer to the Temporary Sector Unprotect algorithm and timing waveforms. A Winbond Company -7Publication Release Date: December 1999 Revision A2 Microelectronics Inc. Read RESET Command BRIGHT BM29F400T/BM29F400B The read or RESET operation is initiated by writing the Read/Reset command sequence in to the command register. Microprocessor read cycles retrieve the data from the memory. The device remains enable for reads until the command register contents are changed. The device will automatically power-up in the Read/Reset mode. In this case, a command sequence is not needed to read the memory data. This default power-up to Read mode ensures that no spurious changes of the data can take place during the power transitions. Refer to the AC Characteristics for Read-Only Operation and the respective Timing Waveforms for the specific timing parameters. Electronic ID Command The BM29F400 contains an Electronic ID command to supplement the traditional PROM programming method described in the Electronic ID Mode section. The operation is initiated by writing the Electronic ID command sequence into the command register. Following command write, a read cycle from address XX00H retrieves manufacturer code of ADH. A read cycle from address XX01H returns the device code (BM29F400T = 23H and BM29F400B = ABH for 8-bit mode; BM29F400T = 2223H and BM29F400B = 22ABH for 16-bit mode) (see Table 3). All manufacturer and device codes exhibit odd parity with the MSB (DQ7) defined as the parity bit. The Electronic ID command can also be used to identify protected sectors. After writing the Electronic ID command sequence, the CPU can scan the sector addresses (see Table 4 and Table 5) while (A6, A1, A0) = (0, 1, 0). Protected sectors will return 01H on the data outputs and unprotected sectors will return 00H. To terminate the operation, it is necessary to write the Read/Reset command sequence into the command register. Byte/Word Programming Command The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation (see Table 6). There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE , whichever happens later, and program data (PD) is latched on the rising edge of CE or WE , whichever happens first. The rising edge of CE or WE , whichever happens first, begins programming using the Embedded Program Algorithm. Upon executing the algorithm, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on DQ7 (also used as Data Polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see Table 7, Write Operation Status Flags). Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time for Data Polling operations. Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during the Internal Program Algorithm will be ignored. If a hardware RESET occurs during the programming operation, the data at that particular location will be corrupted. -8- Microelectronics Inc. BRIGHT BM29F400T/BM29F400B Byte/Word programming is allowed in any sequence, and across sector boundaries. However, remember that a data "0" cannot be programmed to a data "1". Only erase operations can convert a logical "0" to a logical "1". Attempting to program data from "0" to "1" may cause the device to exceed time limits, or even worse, result in an apparent success according to the Data Polling algorithm. In the later case, however, a subsequent read of this bit will show that the data is still a logical "0". Figure 1 illustrates the Byte/Word Programming Algorithm using typical command strings and bus operations. The device will ignore any commands written to the chip during execution of the internal Byte/Word Programming Algorithm. If a hardware RESET occurs during the Byte/Word Programming operation, the data at that particular address location will be corrupted. Chip Erase Command Chip erase is a six bus cycle operation (see Table 6). The chip erase begins on the rising edge of the last WE pulse in the command sequence. Upon executing the Chip Erase command sequence, the device's internal state machine executes an internal erase algorithm. The system is not required to provide further controls or timings. The device will automatically provide adequate internally generated erase pulses and verify chip erase within the proper cell margins. During chip erase, all sectors of the device are erased except protected sectors. During Chip Erase, data bit DQ7 shows a logical "0". This operation is known as Data Polling. The erase operation is completed when the data on DQ7 is a logical "1" (see Write Operation Status section). Upon completion of the Chip Erase operation, the device returns to read mode. At this time, the address pins are no longer latched. Note that Data Polling must be performed at a sector address within any of the sectors being erased and not a protected sector to ensure that DQ7 returns a logical "1" upon completion of the Chip Erase operation. Figure 2 illustrates the Chip Erase Algorithm using typical command strings and bus operations. The device will ignore any commands written to the chip during execution of the internal Chip Erase algorithm. If a hardware RESET occurs during the Chip Erase operation, the data in the device will be corrupted. Sector Erase Command Sector erase is a six bus cycle operation (see Table 6). The sector address (any address location within the desired sector) is latched on the falling edge of WE , while the command data is latched on the rising edge of WE . An internal device timer will initiate the Sector Erase operation 100 S 20% (80 S to 120 S) from the rising edge of the WE pulse for the last Sector Erase command entered on the device. Upon executing the Sector Erase command sequence, the device's internal state machine executes an internal erase algorithm. The system is not required to provide further controls or timings. The device automatically provides adequate internally generated erase pulses and verify sector erase within the proper cell margins. Protected sectors of the device will not be erased, even if they are selected with the Sector Erase command. A Winbond Company -9- Publication Release Date: December 1999 Revision A2 Microelectronics Inc. BRIGHT BM29F400T/BM29F400B Multiple sectors can be erased simultaneously by writing the sixth bus cycle command of the Sector Erase command for each sector to be erased. The time between initiation of the next Sector Erase command must be less than 80 S to guarantee acceptance of the command by the internal state machine. The time-out window can be monitored via the write operation status pin DQ3 (refer to the Write Operation Status section for Sector Erase Timer operation). It is recommended that CPU interrupts be disabled during this time to ensure that the subsequent Sector Erase commands can be initiated within the 100 S window. The interrupts can be re-enabled after the last Sector Erase command is written. As mentioned above, an internal device timer will initiate the Sector Erase operation 100 S 20% (80 S to 120 S) from the rising edge of the last WE pulse. Sector Erase Timer Write Operation Status pin (DQ3) can be used to monitor time out window. If another falling edge of the WE occurs within the 100 mS time-out window, the internal device timer is reset. Loading the sector erase buffer may be done in any sequence and with any number of sectors. Any command other than Sector Erase or Erase Suspend during this period and afterwards will RESET the device to read mode, ignoring the previous command string. Resetting the device with a hardware RESET after it has begun execution of a Sector Erase operation will result in the data in the operated sectors being undefined and may be unrecoverable. In this case, restart the Sector Erase operation on those sectors and attempt to allow them to complete the Erase operation. Command Definitions Device operations are selected by writing specific address and data sequences in to the Command register. Writing incorrect addresses and data values or writing them in the improper sequence will RESET the device to Read mode. Table 5 defines the valid register command sequences. Either of the two Read/Reset commands will RESET the device (when applicable). During Sector Erase operation, data bit DQ7 shows a logical "0". This operation is known as Data Polling. Sector Erase operation is complete when data on DQ7 is a logical "1" (see Write Operation Status section) at which time the device returns to read mode. At this time, the address pins are no longer latched. Note that Data Polling must be performed at a sector address within any of the sectors being erased and not a protected sector to ensure that DQ7 returns a logical "1" upon completion of the Sector Erase operation. Figure 2 illustrates the Sector Erase Algorithm using typical command strings and bus operations. During execution of the Sector Erase command, only the Erase Suspend and Erase Resume commands are allowed. All other commands will RESET the device to read mode. Note: Do not attempt to write an invalid command sequence during the sector erase operation. Doing so will terminate the sector erase operation and the device will /RESET to the read mode. - 10 - Microelectronics Inc. Table 6. Command Definitions Command Sequence Reset/Read Reset/Read Reset /Read Word Byte Word Electronic 4 Bus Write Cycles Required 1 4 First Bus Write Cycle Addr. XXXXH 5555H AAAAH 5555H AAH Data F0H AAH 2AAAH 5555H 2AAAH 55H 55H 5555H AAAAH 5555H Second Bus Write Cycle Addr. Data Third Bus Write Cycle Addr. BRIGHT BM29F400T/BM29F400B Fourth Bus Write Cycle Addr. Data Fifth Bus Write Cycle Addr. Data Sixth Bus Write Cycle Addr. Data Data F0H RA RD 90H 01H(7) 2223H (T Device ID) 22ABH (B Device ID) 23H (T Device ID) ABH (B Device ID) ID Byte AAAAH 5555H AAAAH Program Word Byte 4 5555H AAAAH AAH 2AAAH 5555H 55H 5555H AAAAH A0H PA PD Chip Erase Sector Erase Erase Suspend Erase Resume Word Byte Word Byte Word Byte Word Byte 6 5555H AAAAH AAH 2AAAH 5555H 55H 5555H AAAAH 80H 5555H AAAAH AAH 2AAAH 5555H 55H 5555H AAAAH 10H 6 5555H AAAAH AAH 2AAAH 5555H 55H 5555H AAAAH 80H 5555H AAAAH AAH 2AAAH 5555H 55H SA 30H 1 XXXXH B0H 1 XXXXH 30H Notes: 1. Bus operations are defined in Tables 1 and 2. 2. For a Command Sequence, address bit A15 = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA). 3. RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE . SA = Address of sector to be erased. (See Table 4 for top boot and Table 5 for bottom boot.) 4. The Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. 5. Reading from, and programming to, non-erasing sectors is allowed in the Erase Suspend mode. 6. The System should generate the following address patterns: Word Mode: 5555H or 2AAAH to addresses A0-A14. Byte Mode: AAAAH or 5555H to addresses A-1-A14. 7. Address 00H returns the manufacturer's ID code (Bright Microelectronics - ADH), address 01H returns the device ID code. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the user to interrupt a Sector Erase operation and read data from or to a sector that is not being erased. The Erase Suspend command is applicable only during Sector Erase operation, including, but not limited to, sector erase time-out period after any Sector Erase commands (30H) have been initiated. A Winbond Company - 11 - Publication Release Date: December 1999 Revision A2 Microelectronics Inc. BRIGHT BM29F400T/BM29F400B Writing the Erase Suspend command during the time-out will result in immediate termination of the time-out period. Any subsequent writes of the Sector Erase command will be taken as the Erase Resume command (30H). Note that any other commands during the time-out will RESET the device to the Read mode. The address pins are "don't cares" when writing the Erase Suspend or Erase Resume commands. When the Erase Suspend command is written during a Sector Erase operation, the chip will take between 1 S and 230 S to suspend the erase operation and go into Erase Suspended mode. During this time, the system can monitor the Data Polling or Toggle Bit write operation status flags to determine when the device has entered erase suspend mode (see Write Operation Status section.) The system must use an address of an erasing sector to monitor Data Polling or Toggle Bit to determine if the Sector Erase operation has been suspended. In Erase Suspend mode, the system can read data from any sector that is not being erased. A read from a sector being erased will result in write operation status data. After the system writes the Erase Suspend command and waits until the Toggle Bit stops toggling, data reads from the device may then be performed (see Write Operation Status section). Any further writes of the Erase Suspend command at this time will be ignored. To resume operation of Sector Erase, the Erase Resume command (30H) should be written. Any further writes of the Erase Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed Sector Erase operation. DQ7 Data Polling The BM29F400 device features Data Polling as a method to indicate to the host the status of the Byte/Word Programming, Chip Erase, and Sector Erase operations. When the Byte/Word Programming operation is in progress, an attempt to read the device will produce the compliment of the data last written to DQ7. Upon completion of the Byte/Word Programming operation, an attempt to read the device will produce the true data last written to DQ7. When the Chip Erase or Sector Erase operation is in progress, an attempt to read the device will produce a logical "0" at the DQ7 output. Upon completion of the Chip Erase or Sector Erase operation, an attempt to read the device will produce a logical "1" at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure 3. For Chip Erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For Sector Erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. For both Chip Erase and Sector Erase, Data Polling must be performed at sector address within any of the sectors being erased and not a protected sector. Otherwise, the Data Polling status may not be valid. Once the Internal Algorithm operation is close to being completed, the BM29F400 data pins (DQ7) may change asynchronously while the output enable ( OE ) is asserted low. This means that the device is driving status information on DQ7 at one instant and valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read status or valid data. Even if the device has completed the Internal Algorithm operation and DQ7 has a valid data, data outputs on DQ0-DQ6 may be still invalid. Valid data on DQ0-DQ7 will be read on the successive read attempts. - 12 - Microelectronics Inc. BRIGHT BM29F400T/BM29F400B The Data Polling feature is only active during the Byte/Word Programming operation, Chip Erase operation, Sector Erase Operation, or Sector Erase time-out window (see Table 7). DQ6 Toggle Bit The BM29F400 also features the "Toggle Bit" as a method to indicate to the host system the status of the Internal Programming and Erase Algorithms (see Figure 4 for Toggle Bit (DQ6) flowchart. During an Internal Programming or Erase Algorithm cycle, successive attempts to read ( OE toggling) data from the device will result in DQ6 toggling between one and zero. Once Internal Programming or Erase operation is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During BYTE Programming, Toggle Bit is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For Chip Erase, Toggle Bit is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For Sector Erase, Toggle Bit is valid after the last rising edge of the sector erase WE pulse. Toggle Bit is also active during sector erase timeout window. In Byte/Word Programming, if the sector being written to is protected, the Toggle Bit will toggle for about 300 nS and then stop toggling without the data having changed. In Chip Erase or Sector Erase, the device will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit for about 300 nS and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 Toggle Bit I to toggle. DQ5 Exceeded Timing Limits DQ5 will indicate if the Byte/Word Programming, Chip Erase, or Sector Erase time has exceeded the specified limits (internal pulse count) of the device. Under these conditions DQ5 will produce a logical "1". This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the device under this condition. The OE and WE pins will control the output disable functions as described in Table 1. If this failure condition occurs during Sector Erase operation, it specifies that particular sector is bad and it may not be reused. However, other sectors are still functional and may continue to be used for the program or erase operation. The device must be RESET to the Read mode to use other sectors of the device. Write the Read/Reset command sequence to the device, and then execute the Byte/Word Programming or Sector Erase command sequence. This allows the system to continue to use the other active sectors in the device. If this failure condition occurs during Chip Erase operation, it specifies that the entire chip is bad or combination of sectors are bad. In so, the chip should not be reused. If this failure condition occurs during Byte/Word Programming operation, it indicates the entire sector containing that BYTE is bad and this sector may not be reused (other sectors are still functional and can be reused.) A Winbond Company - 13 - Publication Release Date: December 1999 Revision A2 Microelectronics Inc. BRIGHT BM29F400T/BM29F400B The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case, the device may exceed time limits and not complete the Internal Algorithm operation. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a "1". DQ3 Sector Erase Timer After the completion of the initial Sector Erase command sequence, the sector erase time-out window will begin. DQ3 will remain low until the time-out window is closed. Data Polling and Toggle Bit are valid after the initial Sector Erase command sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, DQ3 maybe used to determine if the Sector Erase time-out window is still open. If DQ3 is a logical "1", the internally controlled erase cycle has begun. Attempts to write subsequent command to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If DQ3 is a logical "0", the device will accept additional Sector Erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. Refer to Table 7: Write Operation Status Flags. Write Operations Status STATUS In Progress Byte/Word Programming Operation Chip or Sector Erase Operation Erase Suspend Mode (Non-Erase Suspended Sector) Exceeded Time Limits Byte/Word Programming Operation Chip or Sector Erase Operation DQ7 DQ7 0 Data DQ7 DQ6 Toggle Toggle Data Toggle Toggle DQ5 0 0 Data 1 1 DQ3 N/A 1 Data 0 1 0 Table 7. Write Operation Status Flags(1) Notes: DQ0, DQ1, DQ4 are reserve pins for future use. RY/BY Ready/Busy Status The BM29F400 provides a RY/BY open-drain output pin as a way to indicate to the host system that an Internal Programming or Erase operation is either in progress or has been completed. If the RY/BY output is low, the device is busy with either a Programming or Erase operation. If the RY/BY output is high, the device is ready to accept a Read, Programming, or Erase command. When the RY/BY pin is low, the device will not accept any additional Programming or Erase commands with the exception of the Erase Suspend command. If the BM29F400 is placed in an Erase Suspend mode, the RY/BY output will be high. - 14 - Microelectronics Inc. BRIGHT BM29F400T/BM29F400B During a programming operation, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. Refer to the timing waveforms for the RY/BY status pin for further clarification. The RY/BY pin is high in the Standby mode. Since this is an open-drain output, several RY/BY pins can be tied together with a pull-up resistor to Vcc. RESET Hardware Reset The BM29F400 device may be RESET by driving the RESET pin to VIL. The RESET pin must be kept low (VIL) for at least 500 nS. Pulling the RESET pin low will terminate any operation in progress. The internal state machine will be RESET to the read mode 1 mS to 230 mS after the RESET pin is driven low. If a hardware RESET occurs during a Programming or Erase operation, the data at that particular location will be indeterminate. When the RESET pin is low and the internal RESET is complete, the device goes to Standby mode and cannot be accessed. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. Once the RESET pin is taken high, the device requires 500 nS of wake up time until outputs are valid for a read access. The RESET pin may be tied to the system RESET input. Therefore, if a system RESET occurs during an Internal Programming or Erase operation, the device will be automatically RESET to read mode. This will enable the system's microprocessor to read the boot-up firmware from the Flag's memory. Data Protection The BM29F400 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power-up the device automatically resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power-up and power-down transitions or system noise. Low Vcc Write Inhibit To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than 3.2V (typically 3.7V). If Vcc < VLKO, the command register is disabled and all internal programming/erase circuits are disabled. Under this condition the device will RESET to the Read mode. Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above 3.2V. Write Pulse "Glitch" Protection Noise pulses of less than 5 nS (typical) on OE , CE or WE will not initiate a write cycle. A Winbond Company - 15 - Publication Release Date: December 1999 Revision A2 Microelectronics Inc. Logical Inhibit BRIGHT BM29F400T/BM29F400B Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE must be a logical "0" while OE is a logical "1". Power-up Write Inhibit Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE . The internal state machine is automatically RESET to the Read mode on power-up. Sector Unprotect The BM29F400 also features a sector unprotect mode, so that protected sectors may be unprotected to incorporate any changes in the code. Protecting all sectors is necessary before unprotecting any sector(s). Sector unprotection is accomplished in a PROM programmer. START Write Program Command Sequence (see below) Data Polling Device NO Increment Address Last Address ? YES Programming Completed Program Command Sequence (Address/Command) 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/ Program Data Figure 1. Internal Programming Algorithm - 16 - Microelectronics Inc. BRIGHT BM29F400T/BM29F400B START Write Erase Command Sequence (see below) Data Polling or Toggle Bit Successfully Completed Erase Completed Individual Sector/Multiple Sector Erase Command Sequence (Address/Command) 5555H/AAH Chip Erase Command Sequence (Address/Command) 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/80H 5555H/80H 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/10H Sector Address/30H Sector Address/30H Additional sector erase commands are optional Sector Address/30H Figure 2. Internal Erase Algorithm A Winbond Company - 17 - Publication Release Date: December 1999 Revision A2 Microelectronics Inc. BRIGHT BM29F400T/BM29F400B START Read Byte (DQ0-DQ7), Addr = VA VA = Byte address for programming = Any of the sector addresses within the secotr being erased during sector erase operation. = XXXXH during Chip Erase DQ7 = Data NO NO DQ5 = 1 YES Read Byte (DQ0-DQ7), Addr = VA YES YES DQ7 = Data Fail Pass Figure 3. Data Polling Algorithm Notes: DQ7 is rechecked even if DQ5 = logical "1" because DQ7 may change simultaneously with DQ5. - 18 - Microelectronics Inc. BRIGHT BM29F400T/BM29F400B START Read Byte(DQ0-DQ7) Addr = Don't care DQ6 = Toggle YES NO DQ5 = 1 ? YES Read Byte (DQ0-DQ7) Addr = Don't care NO DQ6 = Toggle ? YES Fail NO Pass Figure 4. Toggle Bit Algorithm Note: DQ6 is rechecked even if DQ5 = logical "1" because DQ6 may stop toggling at the same time as DQ5 changing to a logical "1". Absolute Maximum Ratings PARAMETER Storage Temperature Plastic Packages Ambient Temperature With Power Applied Voltages with Respect to Ground All pins except A9 (Note 1) Vcc (Note 1); A9 (Note 2) RATING -65 to +125 -55 to +125 -2 to +7 -2 to +7 -2 to +14 200 UNIT C C V mA Output Short Circuit Current (Note 4) Notes : 1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may overshoot Vss to -2.0V for periods of up to 20 nS. Maximum DC voltage on output and I/O pins is Vcc +0.5V. During Voltage transitions, outputs may overshoot to Vcc +2.0V for periods up to 20 nS. 2. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 may overshoot Vss to -2.0V for periods of up to 20 nS. Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods of up to 20 nS. 3. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. A Winbond Company - 19 - Publication Release Date: December 1999 Revision A2 Microelectronics Inc. Operating Ranges PARAMETER Commercial (C) Devices Extended (I) Devices Vcc Supply Voltage Vcc for BM29F400-90 BRIGHT BM29F400T/BM29F400B RATING 0 to +70 -55 to +125 +4.5 to 5.5 UNIT C C V Note: Operating ranges define those limits between which the functionality of the device is guaranteed. *Notice: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Negative Overshoot Waveform 20 nS 20 nS +0.8 V -0.5 V -2.0 V 20 nS Figure 5. Maximum positive Overshoot Waveform Vcc + 2.0 V Vcc + 0.5 V 2.0 V 20 nS 20 nS 20 nS Figure 6. - 20 - Microelectronics Inc. DC CHARACTERISTICS TTL/NMOS Compatible PARAMETER Input Load Current A9 Input Load Current Output Leakage Current VCC Active Current(1) SYM. ILI ILIT ILO ICC1 BRIGHT BM29F400T/BM29F400B TEST CONDITIONS VIN = Vss to VCC, VCC = VCC Max. VCC = VCC Max., A9 = 12.5 V VOUT = Vss to VCC, VCC = VCC Max. CE = VIL, OE = VIH Byte Word MIN. MAX. 1.0 1.0 1.0 40 50 60 1.0 1.0 UNIT A A A mA mA mA mA mA V V V V VCC Active Current(2,3) VCC Standby Current VCC Standby Current (RESET ) Input Low Level Input High Level Voltage for Electronic Output Low Voltage Output High Voltage Notes: ICC2 ICC3 ICC4 VIL VIH VID VOL VOH CE = VIL, OE = VIH VCC = VCC Max., CE = RESET = VIH VCC = VCC Max., RESET = VIL -0.5 2.0 VCC = 5.0V IOL = 5.8 mA, VCC = VCC Min. IOH = -2.5 mA, VCC = VCC Min. 2.4 11.5 0.8 VCC +0.5 12.5 0.45 V 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. ICC active while Internal Algorithm (program or erase) is in progress. 3. Not 100% tested. A Winbond Company - 21 - Publication Release Date: December 1999 Revision A2 Microelectronics Inc. DC Characteristics, continued BRIGHT BM29F400T/BM29F400B CMOS Compatible PARAMETER Input Load Current A9 Input Load Current Output Leakage Current VCC Active Current(1) SYM. ILI ILIT ILO ICC1 TEST CONDITIONS VIN = VSS to VCC, VCC = VCC Max. VCC = VCC Max., A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC Max. CE = VIL, OE = VIH MIN. MAX. 1.0 1.0 1.0 UNIT A A A mA mA mA Byte Word 40 50 60 100 VCC Active Current(2,3) VCC Standby Current ICC2 ICC3 CE = VIL, OE = VIH VCC = VCC Max., CE = VCC 0.5V, RESET = VCC 0.5V A A V V V V V Vcc Standby Current ( RESET ) Input Low Level Input High Level Voltage for Electronic ID and Sector Protect Output Low Voltage Output High Voltage ICC4 VIL VIH VID VOL VOH1 VOH2 VCC = VCC Max., RESET = VSS 0.5V -0.5 0.7 x VCC VCC = 5.0 V IOL = 5.8 mA, VCC = VCC Min. IOH = -2.5 mA, VCC = VCC Min. IOH = -100 mA, VCC = VCC Min. 0.85 x VIH VCC -0.4 3.2 11.5 100 0.8 VCC +0.3 12.5 0.45 V 4.2 V Low VCC Lock-out Voltage Notes: VLKO 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. ICC active while Internal Algorithm (program or erase) is in progress. 3. Not 100% tested. - 22 - Microelectronics Inc. AC CHARACTERISTICS Read-only Operations PARAMETER SYM. JEDEC Standard BRIGHT BM29F400T/BM29F400B DESCRIPTION TEST SETUP -90 -120 -150 UNIT tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCE tOE tHZ tDF tOH Read Cycle Time(2) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z(3,4) Output Enable to Output High Z(2,3) Output Hold Time from Addresses, CE or OE , Whichever Occurs First RESET Pin Low to Read Mode(4) Min. 90 90 90 35 20 20 120 120 120 50 30 30 0 150 150 150 55 35 35 0 nS nS nS nS nS nS nS CE = VIL OE = VIL OE = VIL Max. Max. Max. Max. Min. 0 tREADY tELFL tELFH Max. Max. 20 5 20 5 20 5 mS nS CE to BYTE Switching Low or High Notes: 1. Test Conditions: Output Load: 1 TTL gate and 100 pF Input rise and fall times: 20 nS; Input pulse levels: 0V to 3 V 2. Timing measurement reference level Input/Output: 1.5V 3. Output driver disable time. 4. Not 100% tested. 5.0 V 2.7 KOhm IN3064 or Equivalent DEVICE UNDER TEST CL 6.2 KOhm Diodes = IN3064 or Equivalent Figure 7. Test Condition Note: CL = 100 pF including jig capacitance. A Winbond Company - 23 - Publication Release Date: December 1999 Revision A2 Microelectronics Inc. AC CHARACTERISTICS Programming/Erase Operations PARAMETER JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX BRIGHT BM29F400T/BM29F400B SYM. Standard tWC tAS tAH tDS tDH tOES tOEH DESCRIPTION Write Cycle Time(1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read(1) Toggle & Data Polling(1) -90 -120 -150 UNIT Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Typ. Max. Typ. Max. Typ. Max. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. 90 0 45 45 0 0 0 10 0 0 0 45 20 16 400 0.26 12 2.0 90 50 500 4 500 4 40 4 100 350 4 120 0 50 50 0 0 0 10 0 0 0 50 20 16 400 0.26 12 2.0 90 50 500 4 500 4 50 4 100 350 4 150 0 50 50 0 0 0 10 0 0 0 50 20 16 400 0.26 12 2.0 90 50 500 4 500 4 60 4 100 350 4 nS nS nS nS nS nS nS nS nS nS nS nS nS S S sec sec mS nS mS nS S nS mS mS mS nS tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tWHWH3 tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tWHWH3 tVCS tVIDR tOESP tRP tRSP tBUSY tVLHT tWPP1 tWPP2 tCSP Read Recover Time Before W rite CE Setup Time CE Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation Sector Erase Operation(2) Chip Erase Operation(2) Vcc Setup Time(1) Rise Time to VID(1,3) OE Setup Time to WE Active(1, 3, 4) RESET Pulse Width RESET Setup Time( 3) Programming/Erase Valid to RY/BY Delay(1) Voltage Transition Time(1, 4) Sector Protect Write Pulse Width(4) Sector Unprotect Write Pulse Width(4) CE Setup Time to WE Active(1, 4) Notes: 1. Not 100% tested. 2. Does not include pre-programming time. 3. This timing is for Temporary Sector Unprotect operation. These timings are for Sector Protect and/or Sector Unprotect operations. - 24 - Microelectronics Inc. SWITCHING WAVEFORMS BRIGHT BM29F400T/BM29F400B WAVEFORM INPUT Must Be Steady OUTPUT Will Be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply Will Be Change from H to L Will Be Change from L to H Change, State Unknown Center Line is High impedance Off State t RC Address t ACC CE tHZ OE tOE tDF Address Stable t OEH t OH Output Vaild WE High Z Outputs t CE High Z Figure 8. AC Waveforms for Read Operations A Winbond Company - 25 - Publication Release Date: December 1999 Revision A2 Microelectronics Inc. Switching Waveforms, continued BRIGHT BM29F400T/BM29F400B Data Polling Address 5555H t WC CE tAS PA t AH PA OE tGHWL tWP t WHWH1 tWPH WE tCS tDH Data 5.0V VCC GND A0H tDS PD DQ7 DOUT Figure 9. AC Waveforms Program Operations Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at BYTE address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 6. These waveforms are for 16-bit mode. tAS tAH Address 5555H 2AAAH 5555H 5555H 2AAAH SA CE tGHWL OE tWP WE tWPH tCS Data tDS tVCS 5.0V VCC GND tDH AAH 55H 80H AAH 55H 10H/30H Figure 10. AC Waveforms Chip/Sector Erase Operations Notes: 1. SA is the sector address for Sector Erase. Address = X = Don't Care for Chip Erase. 2. These waveforms are for 16-bit mode. - 26 - Microelectronics Inc. Switching Waveforms, continued BRIGHT BM29F400T/BM29F400B tCH CE t OE OE t OEH WE tCE t OH tDF DQ7 Data DQ0-DQ6 tWHWH 1 or 2 DQ7 DQ7=Valid Data DQ0-DQ7 Valid Data DQ0-DQ6=Invalid tOE High Z 5.0V VCC GND Figure 11. AC Waveforms for Data Polling during Internal Algorithm Operations Note: DQ7 = Valid Data (The device has completed the internal program or erase operation.) CE tOEH OE tOES WE Data Data (DQ0-DQ7) DQ6=Toggle DQ6=Toggle tOE DQ6= Stop Toggling DQ0-DQ7 Valid 5.0V VCC GND Figure 12 AC Waveforms for Toggle Bit during Internal Algorithm Operation Note: DQ6 stops toggling (The device has completed the internal program or erase operation.) A Winbond Company - 27 - Publication Release Date: December 1999 Revision A2 Microelectronics Inc. Switching Waveforms, continued BRIGHT BM29F400T/BM29F400B CE WE The rising edge of the last WE signal Entire programming or erase operations BY/RY 5.0V Vcc GND t BUSY Figure 13. RY/BY Timing Diagram During Program/Erase Operation RY/BY RESET RP Ready t PWH Data 5.0V Vcc Vaild Data GND Figure 14. RESET Timing Diagram - 28 - Microelectronics Inc. Switching Waveforms, continued BRIGHT BM29F400T/BM29F400B tWC Address Address Stable CE tAVFL OE tELFL tDF BYTE tCE Data (DQ0-DQ7) t ACC Data (DQ8-DQ14) tOE tOH Data Output on DQ0-DQ7 Data Output on DQ0-DQ7 High Z Data Outputon DQ8-DQ14 High Z tACC High Z tFLQZ DQ15/A-1 Data Outputon DQ15 High Z Address Input Figure 15. BYTE Timing Diagram for Read Operation CE The falling edge of the last WE signal WE BYTE tSET (tAS ) tHOLD (tAH ) Figure 16. BYTE Timing Diagram for Write Operation A Winbond Company - 29 - Publication Release Date: December 1999 Revision A2 Microelectronics Inc. BRIGHT BM29F400T/BM29F400B Start RESET = V ID (Note 1) Perform Erase or Program Operations RESET = V IH Temporary Sector Unprotect Completed (Note 2) Figure 17. Temporary Sector Unprotect Algorithm Notes: 1. All protected sector groups unprotected. 2. All previously protected sector groups are protected again. 12V RESET tVIDR CE 5V WE tRSP Program or Erase Command Sequence RY/BY Figure 18. Temporary Unprotect Timing Diagram - 30 - Microelectronics Inc. AC CHARACTERISTICS Programming/Erase Operations PARAMETER JEDEC tAVAV tAVEL tELAX tDVEH tEHDX SYM. Standard tWC tAS tAH tDS tDH tOES tOEH Write Cycle Time(1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time(1) Output Enable Hold Time tGHWL tWLEL tEHWH tELEH tEHEL tWHWH1 tGHWL tWS tWH tCP tCPH tWHWH1 Read(1) DESCRIPTION BRIGHT BM29F400T/BM29F400B -90 Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Typ. Max. 90 0 45 45 0 0 0 10 0 0 0 45 20 16 400 0.26 12 2.0 90 50 500 4 100 10 4 4 -120 120 0 50 50 0 0 0 10 0 0 0 50 20 16 400 0.26 12 2.0 90 50 500 4 100 10 4 4 -150 150 0 50 50 0 0 0 10 0 0 0 50 20 16 400 0.26 12 2.0 90 50 500 4 100 10 4 4 Unit nS nS nS nS nS nS nS nS nS nS nS nS nS mS mS sec sec sec sec mS nS mS mS mS mS nS Toggle and Data Polling(1) Read Recover Time Before W rite WE Setup Time WE Hold Time CE Pulse Width CE Pulse Width High Byte Programming Operation tWHWH2 tWHWH2 Sector Erase Operation(2) Typ. Max. tWHWH3 tWHWH3 Chip Erase Operation(2) Typ. Max. tVCS tVIDR tVLHT tWPP1 tWPP2 tOESP tCSP Vcc Setup Time(1,3) Rise Time to VID(1,3) Voltage Transition Time(1,3) Sector Protect Write Pulse Width(4) Sector Unprotect Write Pulse Width(4) Min. Min. Min. Min. Min. Min. Min. OE Setup Time to WE Active(1, 3) OE Setup Time to WE Active(1, 4) Notes: 1. Not 100% tested. 2. Does not include pre-programming time. 3. This timing is for Sector Unprotect operation. 4. Output Driver Disable Time. A Winbond Company - 31 - Publication Release Date: December 1999 Revision A2 Microelectronics Inc. Switching Waveforms, continued BRIGHT BM29F400T/BM29F400B Data Polling Address 5555H t WC t AS CE t GHWL PA t AH PA OE t WP t WHWH1 t WPH t CS tD H WE Data A0H t DS PD DQ7 DOUT 5.0V Vcc GND Figure 19. Alternate CE Controlled Program Operation Timings Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at BYTE address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 6. These waveforms are for the x16 mode. - 32 - Microelectronics Inc. Erase and Programming Performance PARAMETER MIN. Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles 10,000 BRIGHT BM29F400T/BM29F400B LIMITS TYP. 0.33 2.4 16 8 100,000 MAX. 15 120 400 200 UNIT sec sec S sec cycles Latch Up Characteristics PARAMETER Input Voltage with respect to Vss on all I/O pins Vcc Current MIN. -1.0V -100 mA MAX. Vcc + 1.0V + 100 mA Note: Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. CAPACITANCE TSOP Pin PARAMETER Input Capacitance Output Capacitance Control Pin Capacitance Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25, f = 1.0 MHz. SYMBOL CIN COUT CIN2 TEST SETUP VIN = 0 VOUT = 0 VIN = 0 TYP. 6 8.5 8 MAX. 7.5 12 10 UNIT pF pF pF Data Retention PARAMETER Minimum Pattern Data Retention Time Minimum Pattern Data Retention Time TEST CONDITIONS 150 125 MIN. 10 20 UNIT Years Years A Winbond Company - 33 - Publication Release Date: December 1999 Revision A2 Microelectronics Inc. ORDERING INFORMATION PART NO. ACCESS TIME (nS) 29F400T-90TC 29F400T-12TC 29F400B-90TC 29F400B-12TC Notes: BRIGHT BM29F400T/BM29F400B POWER SUPPLY CURRENT MAX. (mA) 60 60 60 60 BOOT BLOCK PACKAGE CYCLING TEMPERATURE (MIN.) RANGE 90 120 90 120 Top Top Bottom Bottom 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 10,000 10,000 10,000 10,000 0C-70C 0C-70C 0C-70C 0C-70C 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. Typical Program/Erase Cycle is 100,000. - 34 - Microelectronics Inc. APPENDIX A: Compatibility to AMD's AMD29F400B: BRIGHT BM29F400T/BM29F400B The device is essentially fully functional compatible to the AMD29F400B except for three issues: 1. During Erase Suspend 2. DQ2 Status Flag 3. Command Address Subset During Erase Suspend, the device can only read data in the memory-- not Program or execute an Auto Command like the AMD29400B. Also, the DQ2 Flag is not available. This flag is used to determine during multiple or single sector erase whether a sector has been selected for erase. DQ2 can only be used during and embedded sector erase operation or during erase suspend. In the AMD device, commands do not require address pin A15, A14, A13, A12, A11 to be forced during the command sequence. This makes their device slighly easier to inadvertently create a command and cause a program, erase or malfunction. The advantage of reducing the address to a subset is to simplify the hardware interface in systems where control signals are limited in number. The 29F400B reduces the interface requirement by 4 signals. However if the full address is supplied (i.e.2AAAH and 5555H) by the host system, there will be no incompatibility using either device. A Winbond Company - 35 - Publication Release Date: December 1999 Revision A2 Microelectronics Inc. PACKAGE DIMENSIONS TSOP48 BRIGHT BM29F400T/BM29F400B 48-pin Standard Thin Small Outline Package (measured in millimeters) 0.95 1.05 Pin 1 I.D. 1 48 11.90 12.10 0.50 BSC 24 18.30 18.50 19.80 20.20 25 0.05 0.15 1.20 MAX 0.25MM(0.0098)BSC 0 5 .050 .070 0.08 0.20 0.10 0.21 - 36 - Microelectronics Inc. VERSION HISTORY VERSION A1 A2 DATE May 1999 Dec. 1999 PAGE 1, 3, 34, 35, 37 21, 35 23 BRIGHT BM29F400T/BM29F400B DESCRIPTION Initial Issued Remove PSOP package Remove industrial specifications Change AC Testing Input level from 0.45V/2.4V to 0V/3V and Input/Output Reference level to 1.5V Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. A Winbond Company - 37 - Publication Release Date: December 1999 Revision A2 |
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